This invention relates generally to complex multichip modules (MCMs) and, more particularly, to complex MCMs which can cost-effectively be assembled with high yields, as well as to corresponding methods of manufacture.
As disclosed in Eichelberger et al U.S. Pat. No. 4,783,695, and subsequent related patents, some of which are referred to herein below, high density interconnect (HDI) technology has quite successfully been employed to interconnect large numbers of complex semiconductor devices to make multichip modules, with improved electrical, thermal, and mechanical performance characteristics, compared to various other single chip and multichip packaging approaches. Very briefly, HDI MCMs include a plurality of semiconductor integrated circuit chips and other electronic components mounted on a substrate. The chips and other electronic components are interconnected by a multilayer interconnect structure including interleaved layers of thin film polymer dielectric material (e.g. KAPTON.RTM. polyimide--KAPTON is a trademark of Dupont Co.) and patterned metallization, with vias formed in the polymer layers.
A broad spectrum of modules have been successfully fabricated using this HDI technology. These include high chip count modules (including 40 to 50 chips), high pin count modules (with 400 I/O lines), high speed digital modules (200 MHz on Si, and 2 Ghz on GaAs), mixed analog and digital modules (e.g. 44 channel A/D conversion modules), power conversion modules (e.g. 50V to 5V DC to DC), microwave modules (S, C, Ku and X-band) and millimeter wave modules (44 Ghz).
More particularly, the previously-disclosed HDI structure employs a ceramic substrate, made of alumina, for example, with a thickness between 25 and 100 mils. The substrate is of appropriate size and strength for the overall electronic system in which it is utilized. This size is typically on the order of two inches square.
Individual cavities, or one large cavity, having appropriate depths at the intended locations of the various chips, are prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, laser or ultrasonic milling is used to form the cavities in which the various chips and other components are subsequently positioned. For systems where it is desired to place chips of uniform size edge-to-edge, a single large cavity may be satisfactory.
The various components are placed in their desired locations within the cavities and adhered by means of a thermoplastic adhesive layer, preferably ULTEM.RTM. polyetherimide resin (ULTEM is a trademark of General Electric Co.). More particularly, the entire structure is heated to the softening point of the ULTEM polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C. depending on the formulation used) and then cooled to thermoplastically bond the individual components to the substrate. At this stage, the upper surfaces of all components and the substrate are disposed in a substantially common plane.
The multilayer interconnect overcoat structure is then built up to electrically interconnect the components into an actual functioning system. To begin the HDI overcoat structure, a polyimide dielectric film, which may be KAPTON.RTM. polyimide, about 0.0005 to 0.003 inch (12.5 to 75 microns) thick is pretreated to promote adhesion and coated on one side with ULTEM polyetherimide resin or another thermoplastic and laminated across the top of the chips, other components and the substrate, with the ULTEM resin serving as a thermoplastic adhesive to hold the KAPTON film in place.
The actual as-placed locations of the various components and contact pads thereon are determined, and via holes are adaptively laser drilled in the KAPTON film and ULTEM adhesive layers in alignment with the contact pads on the electronic components. Exemplary laser drilling techniques are disclosed in Eichelberger et al U.S. Pat. Nos. 4,714,516 and 4,894,115; and in Loughran et al U.S. Pat. No. 4,764,485.
A metallization layer is deposited over the KAPTON film layer and extends into the via holes to make electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it, or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser which is scanned relative to the substrate to provide an accurately aligned conductor pattern at the end of the process. Exemplary techniques for patterning the metallization layer are disclosed in Wojnarowski et al U.S. Pat. Nos. 4,780,177 and 4,842,677; and in Eichelberger et al U.S. Pat. No. 4,835,704 which discloses an "Adaptive Lithography System to Provide High Density Interconnect." Any misposition of the individual electric components and their contact pads can be compensated for by and adaptive laser lithography system as disclosed in U.S. Pat. No. 4,835,704.
Additional dielectric and metallization layers are provided as required in order to make all of the desired electrical connections among the chips.
Yield and cost considerations have been important factors in the fabrication of such HDI modules. Thus, due in part to the varying die yields of the individual semiconductor die, initial module yields following initial assembly, which may be viewed as the first pass, range from 25% to 90%. With the implementation of module rework and repair, final module yields were improved to 80% to 100%.
An HDI module can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. Repairability is particularly important where fifty or more chips having a cost of as much as $2,000.00, each, may be incorporated in a single system on one substrate. Techniques for testing and repairing HDI MCMs are disclosed in Eichelberger et al U.S. Pat. Nos. 4,878,991, 4,884,112 and 4,937,203; and in Wojnarowski et al U.S. Pat. No. 5,154,793.
One key element to the repair of a failing HDI MCM as disclosed in those patents is that the adhesive which attaches the first layer of the overlay to the components, and the adhesive which attaches the components to the substrate, are both thermoplastic polymers that soften and release when exposed to an elevated temperature. Another key to the disclosed rework process is that the adhesive which attaches the overlay softens at a lower temperature than the adhesive which attaches the die or other components. Thus, by raising a defective module to a temperature above the overlay adhesive softening temperature, but below the die attach adhesive softening temperature, the overlay structure can be removed from the substrate without disturbing the chips below. To subsequently remove a chip, localized heat is applied to the selected chip raising the temperature of the chip above the softening temperature of the die attach adhesive, and permitting chip removal by a number of manual methods.
The module is then repaired by adhesive clean up, reapplication of a die adhesive, placement of the replacement die and curing of the die attach adhesive. This is followed by repeating all of the overlay thin film processing steps.
A subsequent technology, known as COF (Chip On Flex) was developed to reduce the complexity and cost of the HDI process, in two respects.
In overview, a first aspect of the COF technology, as disclosed in Fillion et al U.S. Pat. Nos. 5,353,498 and 5,497,033, is that the HDI ceramic substrate milling process is eliminated by employing a molding process. Thus, the die top surfaces (which support component connection pads) are bonded to a polymer stretched film, employing a thermoplastic or thermoset adhesive, and then a polymeric molding material, such as an epoxy-based molding compound, is employed to encapsulate all remaining surfaces of the chips and other electronic components. The chips and other electronic components are thus encapsulated within a body of hardened epoxy-based molding compound, which forms the substrate.
In overview, a second aspect of the COF technology, as discussed in Fillion et al U.S. Pat. No. 5,353,195 with respect to power and to signal connections, is that a polymer dielectric stretched film which is pre-patterned on either or both sides is used to provide two interconnect layers that do not require the relatively expensive HDI thin film processing steps summarized hereinabove.
The overlay structure is then completed employing the previously-disclosed HDI thin film processing techniques, using a laser to form via holes, and forming a third patterned metallization layer, including connections through the vias to the component connection pads.
More particularly, as the COF process is generally implemented, a polymer film structure comprises a polyimide film of uniform thickness, which may be within the range of 10 to 100 microns, having a pattern of metallization on the top surface, bottom surface, or both surfaces. Typical metallization thickness is within the range of 1 to 200 microns, and the metallization comprises Cu or Al, and a barrier layer metal such as Ti or Cr. A polymer adhesive is coated over either selected areas of or the entire surface of the bottom side of the polymer film structure. The polymer adhesive may be a thermoset or a thermoplastic material.
At least one component is mounted to the bottom side of the polymer film structure, with a top (active) surface of the component (or components) in contact with the polymer adhesive and mechanically bonded to the polymer film structure by the adhesive. The component is then encapsulated along its bottom and side surfaces within a body of plastic molding compound that also covers at least a portion of the adhesive-coated bottom side of the polymer film structure. The molding compound is a thermoset polymer, such as a epoxy with low CTE (coefficient of thermal expansion) particles mixed within it.
Vias are then formed through the polymer film, aligned with respective component contact pads on the top surface of the component. In addition, at least one via extends through the polymer film to the metallization on the bottom surface of the polymer film structure. Vias may be formed by laser ablation, plasma etching, chemical etching, mechanical milling, or by a combination of these methods. Finally, an upper metallization layer is formed and patterned, extending through the vias to electrically contact the component contact pads and the metallization on the bottom surface of the polymer film structure, and to leave contact pads on the top surface.
The resultant structure can have three layers of interconnection, but advantageously only one of these layers requires the HDI thin film processing steps at the time of assembly. A disadvantage however is that the encapsulated molding step makes reworking or repair of a COF module that happen to have a defective die difficult and costly, or even impossible.
The COF technology accordingly is particularly applicable to simple high-yielding few-chip modules. The COF technology, despite its cost advantages, is not as useful with more complex MCMs in view of yield issues.